SECQAI Ltd
Ultra-secure semiconductor solutions company SECQAI has successfully finished the tape-out of its ground-breaking SE01 “Q-Locked” CHERI ISA V9 Trusted Platform Module (TPM), making a historic announcement that might redefine the parameters of digital security. Fabricated using TSMC’s cutting-edge 22nm technology, this accomplishment represents a turning point for the commercialization of scalable computer that is intrinsically memory-safe and resistant to upcoming quantum attacks. Capability Hardware Enhanced RISC Instructions (CHERI) and Post-Quantum Cryptography (PQC), two of the most powerful security paradigms, are combined into a single deployable hardware primitive in SECQAI, creating a strong new foundation for hardware trust in the world’s digital infrastructure.
The tape-out on TSMC’s industry-leading 22nm process is not just a technical accomplishment; it also confirms that the design is ready for large-scale deployment and mass production. This accessibility is critical because widespread hardware-level adoption is needed to secure the digital future, especially in critical national infrastructure (CNI) and emerging industries like artificial intelligence (AI) infrastructure where data secrecy and computational integrity are critical.
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The Dual-Security Revolution: Addressing Present and Future Threats
Cryptographic integrity and platform authenticity are the cornerstones of the contemporary digital economy, which includes cloud servers, financial systems, and ubiquitous consumer gadgets. These functions are often performed by the Trusted Platform Module (TPM). To guarantee the integrity and authenticity of hardware platforms, secure cryptographic key generation and storage, and the verification of a device’s identity (authentication) while maintaining its own internal integrity (that it hasn’t been tampered with), the TPM is an essential security primitive.
The danger landscape has changed, though, and now consists of two distinct challenges: the existential threat of cryptographically-relevant quantum computers (CRQCs) and the persistent, systemic scourge of memory-related attacks. Both are concurrently addressed by SECQAI’s “Q-Locked” SE01 device, which is a quantum-secure firewall based on a memory-hardened architecture. In order to solve the large number of memory flaws that allow cyberattacks on a daily basis, the firm created the “Q-Locked” line. At the same time, it offered the hardware capacity required for clients to use PQC on a large scale.
Hardening the Present: Eliminating Memory Vulnerabilities with CHERI
Memory security has been the weak point of computing for many years. Numerous studies, including those conducted by Microsoft, show that memory safety flaws are the cause of about 70% of all known Common Vulnerabilities and Exposures (CVEs). Hackers can obtain unauthorized access, run malicious code, and eventually take over a system with these vulnerabilities, which include common attack vectors like buffer overflows, use-after-free issues, and integer overflows.
The answer goes beyond simple software fixes and necessitates a complete overhaul of the hardware’s memory pointer management. Herein lies the breakthrough solution offered by the Capability Hardware Enhanced RISC Instructions (CHERI) architecture.
CHERI, which was created in partnership with SRI International and pioneered by the Department of Computer Science and Technology at the University of Cambridge, expands upon the widely used RISC-V Instruction Set Architecture (ISA).
Hardware-enforced descriptors that are unforgeable are embedded into each memory reference by CHERI. A capability specifies a memory block’s address while crucially enforcing fine-grained restrictions on how that memory can be accessed, including its size and the permitted activities (read, write, execute).
The internal operation of the SECQAI Q-Locked TPM is essentially memory-safe due to its implementation of the commercially available CHERI ISA v9. When a piece of code tries to access memory above its specified limits, the hardware steps in and immediately terminates the process. By significantly reducing the attack surface, this architectural resilience changes the security paradigm from “detect and patch” to “secure by design,” making the great majority of existing software vulnerabilities irrelevant for the TPM’s safe operation.
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Future-Proofing Cryptography: PQC Imperative and Hardware Acceleration
In addition to strengthening the present, SECQAI is getting gadgets ready for the future. RSA and Elliptic Curve Cryptography (ECC), which safeguard everything from web traffic to cryptocurrency transactions, are at risk of being completely destroyed by the imminent reality of quantum computers that can execute Shor’s and Grover’s algorithms. Under the direction of the U.S. National Institute of Standards and Technology (NIST), the shift to Post-Quantum Cryptography (PQC) new cryptographic primitives that are immune to quantum attacks is an internationally acknowledged necessity.
The SE01 Q-Locked TPM is specifically made to speed up the hardware implementation of these novel, computationally demanding PQC algorithms. FIPS 203, 204, and 205 designate the set of NIST-approved PQC algorithms that it supports. Lattice-based systems such as CRYSTALS-Dilithium for digital signatures and CRYSTALS-Kyber for key encapsulation are examples of these. PQC algorithms are more computationally demanding than their classical counterparts, despite being quantum-resistant.
In high-speed systems like commercial servers and next-generation AI accelerators, SECQAI guarantees that the PQC transition may be completed effectively without causing intolerable latency or power consumption problems by incorporating the acceleration directly into the TPM hardware.
Additionally, the chip satisfies the strict requirements for cryptographic modules used by regulated businesses and governments around the world with its design in accordance with FIPS 140-3 regulations.
Forging the Path to Global Adoption
The commercial and strategic ramifications of this tape-out make it significant. SECQAI is offering Original Equipment Manufacturers (OEMs) a conveniently scalable component on the 22nm commercial foundry process by introducing a CHERI-enabled, PQC-accelerated TPM. An important step in democratizing advanced hardware security is the ability to incorporate this component across their whole product range, which includes anything from mass-market consumer devices to business systems. By confirming the legitimacy and integrity of commercial servers and AI infrastructure before they ever start to boot, the SE01 chip is made especially to act as the foundation of confidence.
The teamwork that lead to this innovation was highlighted by Rahul Tyagi, CEO of SECQAI: “They are excited to have reached this significant milestone. To meet the urgent need for more secure chips on the market, they have collaborated closely with a major OEM partners. The successful launch of this ground-breaking technology has been made possible by the partnership with TSMC and their VCA IMEC. They are eager to collaborate with the industry to facilitate the broad implementation of secure, memory-safe compute.
A significant milestone for safe computing has been reached with the successful tape-out of SECQAI’s Q-Locked CHERI TPM, which provides a practical and expandable answer to the two most important hardware security issues of a time: memory vulnerability and the quantum threat. Through the provision of architectural defense and hardware-level acceleration for PQC through CHERI, SECQAI is giving OEMs the resources they need to future-proof their systems and devices, opening the door for reliable cloud services and AI.
