With significant certification advancements and a thorough 2026 roadmap, SEALSQ speeds up the global transition to post-quantum security.
Quantum-resistant secure element QS7001 SEALSQ
SEALSQ Corp (NASDAQ: LAES) has announced important accomplishments in its security certification programs, which further clarify the worldwide roadmap for quantum-resistant infrastructure. The company announced that it had obtained an unqualified renewal for its IC’Alps site certification and successfully passed the most stringent hardware security tests for its flagship QS7001 Secure Element platform.
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These accomplishments, together with a recently released ambitious development roadmap, position SEALSQ at the forefront of the shift to Post-Quantum Cryptography (PQC) as quantum computing grows.
Overcoming the “Gold Standard” of Hardware Testing
The QS7001 Secure Element’s ability to pass fault injection and side-channel attack resistance testing is the most noteworthy technological accomplishment that has been revealed. These tests, which are the most rigorous physical security evaluations in the Common Criteria (CC) EAL 5+ evaluation procedure, are carried out by the independent assessor SERMA.
By monitoring power usage, electromagnetic emissions, or purposefully causing problems in a chip’s operation, hackers can harvest critical information using sophisticated, practical techniques like side-channel and fault injection attacks. The QS7001 platform has demonstrated its resilience against these sophisticated attack methods by obtaining a “PASS” result. This achievement confirms that SEALSQ’s PQC hardware can endure the greatest levels of physical examination needed by international standards, marking a critical turning point for the company.
IC’Alps Site Renewal: Strengthening the Design Perimeter
The design environment’s security is just as important as the hardware’s resilience. At its design center in Grenoble, France, IC’Alps, a subsidiary of SEALSQ, has successfully finished its Common Criteria site certification renewal assessment. This renewal, carried out by SERMA CESTI, attests to the Group’s design skills’ operational maturity and security.
This “site certification” guarantees the chip’s whole lifecycle, from basic design to final architecture, is managed inside a perimeter that complies with stringent international security regulations. This result gives clients an end-to-end chain of confidence and reinforces SEALSQ’s integrated certification perimeter.
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The Roadmap for 2026: A Clear Route to Compliance
SEALSQ released a comprehensive certification and manufacturing schedule for its two main secure hardware product families, the QS7001 Secure Element and the QVault Trusted Platform Module (TPM), in conjunction with these milestones. As of right now, all four of these items have “green status,” meaning they are on track.
The QS7001 Series:
- QS7001 V1: Production samples were made available in March 2026, and the certification process is still proceeding as planned.
- QS7001 V2: Complete post-quantum cryptography API security is included in this release. With a planned “fab-out” date of April 21, 2026, wafer production is currently under progress. Full production samples are scheduled by October 2026, with engineering samples anticipated by July 2026.
The QVault TPM Series:
- QVault TPM 183: March 2026 saw the release of production samples. In September 2026, the business plans to submit a FIPS 140-3 lab to NIST, and in October of the same year, it hopes to receive TCG certification.
- QVault TPM 185: With complete post-quantum support, this product was created especially for the PC/server and IoT industries. Engineering samples are anticipated in July 2026. It is scheduled for FIPS submission and TCG certification in late 2026, much as its twin.
The flash-based architecture of the QS7001 series is a crucial characteristic that enables safe over-the-air firmware upgrades. This guarantees that devices won’t need to change their actual hardware in order to retain long-term lifecycle resistance against changing threats.
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Sealsq’s new QS7001 chip offers immediate CNSA 2.0 compliance
These certificates’ timing is not accidental. To protect sensitive data against future quantum computers, which will be able to crack conventional encryption techniques like RSA and Elliptic Curve Cryptography (ECC), governments and commercial businesses are racing against the clock.
Governments and enterprises are facing real migration deadlines, including the NSA CNSA 2.0 January 2027 compliance timeline, and certified silicon is not optional, stated Carlos Moreira, CEO of SEALSQ, emphasizing the significance of predictability in this transformation. To facilitate the seamless transition to PQC for infrastructure providers and device manufacturers, SEALSQ maintains this timetable across four product lines concurrently.
These independently confirmed CC and FIPS certifications are crucial for industries including financial services, medical systems, defense, and smart energy. By positioning its clients ahead of projected industry-wide assessment delays, SEALSQ’s early FIPS 140-3 submission method lowers procurement risks throughout the worldwide cryptography shift.
Greater Strategic Impact
These certification achievements come after a time of high activity for SEALSQ. The corporation released its audited FY 2025 financial reports in late March 2026, revealing $18 million in revenue, a 66% increase over the previous year. Additionally, SEALSQ and Kaynes Semicon made a major entry into the South Asian market on April 1, 2026, when they opened India’s first Post-Quantum Cryptography Personalization Center in Gujarat.
SEALSQ is building a “future-proof” barrier for vital applications like industrial automation, automotive systems, and Multi-Factor Authentication (MFA) tokens as it continues to include post-quantum cryptography into its semiconductor products. The business is successfully anchoring the next generation of digital security in validated, post-quantum silicon with the QS7001 and QVault TPM families, which are slowly approaching final certification.
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